Research and development on various kinds of nonvolatile memory (nonvolatile semiconductor memory device) have been promoted recently, and among them, an MRAM (Magneto-resistance Random Access Memory), OUM (Ovonic Universal memory), a PRAM (Phase-change Random Access Memory) and an RRAM (Resistance Random Access Memory) that read a difference in resistance value as data have the advantages that there is no statistical physical limit regarding scaling.
In general, the PRAM and the RRAM are provided with a nonvolatile variable resistance element whose resistance value is changed when a voltage pulse having a certain threshold value or more is applied, and include a memory cell array having memory cells each including a variable resistance element without a selection element such as a transistor and a diode. Here, FIG. 2 is a schematic view showing one constitution example of the memory cell array. A memory cell array 100 is constituted such that memory cells each having a variable resistance element 103 are arranged in a row direction and a column direction, one end of each of the variable resistance elements 103 arranged in the same row is connected to a word line 102, and one end of each of the variable resistance elements 103 arranged in the same column is connected to a bit line 101. A resistance value of the variable resistance element 103 is changed when the potential difference between the bit line 101 and the word line 102 becomes higher than a certain threshold value VTH.
FIG. 13 shows one example of a memory cell array 200 including no selection element. The memory cell array 200 is a cross point type memory in which a variable resistor 202 and an upper electrode 203 that intersect with a lower electrode 201 at right angles are laminated on the lower electrode 201. Since the selection element is not used, an area occupied by a memory cell can be small, so that the memory has large capacity. Furthermore, since such cross point type memory is simple in structure, a multilayer structure can be easily provided and a high-integrated memory can be implemented.    Patent document 1: U.S. Pat. No. 6,204,139B1    Patent document 2: Japanese Laid-Open Patent Publication No. 2003-338607